Building with make

Why make?

Typing gcc commands for ten files is tedious and error-prone, and recompiling everything after editing one file wastes time. make compares file modification times: if tax.c is newer than tax.o, it recompiles tax.c and relinks, and leaves everything else alone.

A first Makefile

# Makefile
CC = gcc
CFLAGS = -std=c17 -Wall -Wextra -g

billing: main.o tax.o invoice.o
	$(CC) $(CFLAGS) main.o tax.o invoice.o -o billing

main.o: main.c tax.h invoice.h
	$(CC) $(CFLAGS) -c main.c

tax.o: tax.c tax.h
	$(CC) $(CFLAGS) -c tax.c

invoice.o: invoice.c invoice.h tax.h
	$(CC) $(CFLAGS) -c invoice.c

.PHONY: clean
clean:
	rm -f *.o billing

make            # builds the first target (billing)
make clean      # runs the clean recipe
make -j4        # build up to 4 targets in parallel

How make decides

1. To build billing, it first makes sure main.o, tax.o and invoice.o are up to date.
2. tax.o depends on tax.c and tax.h: if either is newer than tax.o (or tax.o is missing), it runs the recipe.
3. If any .o changed, billing is relinked.
4. Edit only tax.c → only tax.o is rebuilt and billing relinked.

Pattern rules and automatic variables

CC = gcc
CFLAGS = -std=c17 -Wall -Wextra -g
OBJS = main.o tax.o invoice.o

billing: $(OBJS)
	$(CC) $(CFLAGS) $^ -o $@

%.o: %.c
	$(CC) $(CFLAGS) -c $< -o $@

.PHONY: clean
clean:
	rm -f $(OBJS) billing

The pattern rule above does not know that main.o also depends on tax.h, so editing a header might not trigger a rebuild. Real projects add automatic dependency generation (gcc -MMD -MP) or list header dependencies explicitly.

Beyond make

Larger and cross-platform projects often use CMake, which generates Makefiles (or Ninja or Visual Studio files) from a CMakeLists.txt description. You will still meet plain Makefiles everywhere in the Linux and embedded world, so knowing them pays off.